Télécharger le livre :  ASIC and FPGA Verification
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays...

Editeur : Morgan Kaufmann
Parution : 2004-10-23
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