Téléchargez le livre : Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog

Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog



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Éditeur :

Kluwer Academic Publishers


Paru le : 2000



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Description

Explaining how you can write Verilog to describe chip designs at the RT-level in a manner that co-operates with verification processes, this text focuses on how this co-operation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labour costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process.
Pages
n.c
Collection
n.c
Parution
2000
Marque
Kluwer Academic Publishers
EAN papier
0306470160
EAN PDF
0306470160
Informations sur l'ebook
Nombre pages copiables
1
Nombre pages imprimables
10
Taille du fichier
1445 Ko
Ce livre est accessible aux handicaps Voir les informations sur l'accessibilité
Prix
132,25 €

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